Georgios Vavouliotis

Georgios Vavouliotis

PostDoctoral Researcher @ Huawei Zurich Research Center

About Me

My name is Georgios (Yorgos) Vavouliotis and I am a Postdoctoral Researcher at Huawei Research Center in Zurich. I received my Ph.D. from Universitat Politècnica de Catalunya (UPC) and Barcelona Supercomputing Center (BSC-CNS), supervised by Marc Casas and Lluc Alvarez, while closely collaborating with Daniel A. Jiménez from Texas A&M University, Boris Grot from University of Edinburgh, and Paul Gratz from Texas A&M University. I also hold a diploma on Electrical and Computer Engineering from the National Technical University of Athens (NTUA).

My research interests include all shades of computer architecture. I am currently conducting microarchitectural research aimed at reducing the address translation overheads, enhancing the efficacy of cache prefetchers, improving cache/TLB management for emerging applications with large data and code footprints, leveraging ML to build intelligent microarchitectural components, and re-thinking microarchitectural designs for server and data center applications.

My research work has received accolades, including Best Paper and Best Poster awards, and has been featured in top-tier computer architecture conferences, including ISCA, HPCA, and MICRO.

You can find my research vision for the next years here [updated Feb 2023].

Recent News

[2024] I will serve in the MICRO 2024 Program Committee (PC).

[2024] I will serve in the ASPLOS 2025 Program Committee (PC).

[2024] I will serve in the ISCA 2024 Industry Track Program Committee (PC).

[2024] Our paper entitled Practically Tackling Memory Bottlenecks of Graph-Processing Workloads got accepted at IPDPS 2024.

[2024] Our paper entitled A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering got accepted at HPCA 2024.

[2024] I will serve in the Program Committee (PC) of the European Conference on Parallel and Distributed Computing (Euro-Par’24).

[2023] I will serve in the Artifact Evaluation (AE) Committee of HPCA '24.

[2023] I will serve as Website Co-Chair at ISCA '24.

[2023] I succefully defended my Ph.D. entitled Advanced Hardware Prefetching in Virtual Memory Systems receiving the Cum Laude Award.

[2023] I received the Hisilicon Core Star Award from Huawei.

[2023] Our paper Concurrent GCs and Modern Java Workloads: A Cache Perspective received the Best Paper Award at ISMM '23.

[2023] Our paper Concurrent GCs and Modern Java Workloads: A Cache Perspective got accepted at ISMM '23.

[2023] Page Size Aware Cache Prefetching, our recent MICRO '22 paper, received the HiPEAC 2022 Paper Award.

[2023] I will join Huawei ZRC in Zurich as a Postdoctoral Researcher on February.

[2023] I'll give a talk about Hardware Prefetching in Virtual Memory Systems at the 6th Computing Systems Research Day in Athens.

[2022] Our paper Page Size Aware Cache Prefetching was selected among the most interesting MICRO '22 papers from Denis Bakhvalov.

[2022] I received the MICRO '22 Student Travel Grant and I'll physically attend the MICRO '22 conference in Chicago.

[2022] Our paper Page Size Aware Cache Prefetching got accepted at MICRO 2022.

[2022] I presented a poster of our ISCA '21 paper Exploiting Page Table Locality for Agile TLB Prefetching at ISCA '22 in New York.

[2022] I received the ISCA '22 Student Travel Grant and I'll physically attend the ISCA '22 conference in New York.

[2022] Morrigan, our recent MICRO '21 paper, received the HiPEAC 2021 Paper Award.

[2022] Exploiting Page Table Locality for Agile TLB Prefetching, our recent ISCA '21 paper, received the HiPEAC 2021 Paper Award.

[2021] I'll give a talk about Morrigan, our recent MICRO '21 paper, at Huawei Zurich.

[2021] I'm joining the Huawei Zurich Research Center for a 6-month internship to work on memory management.

[2021] Our poster Leveraging Page Size Information to Enhance Data Cache Prefetching was selected to participate in the 2021 ACM Student Research Competition (SRC). (certificate)

[2021] Our paper Morrigan: A Composite Instruction TLB Prefetcher got accepted at MICRO 2021.

[2021] Our poster Leveraging Page Size Information to Enhance Data Cache Prefetching received the Best Poster Award at 2021 ACM Summer School on HPC Architectures for Artificial Intelligence and Dedicated Applications, and was awarded with 500$.

[2021] I'll attend the 2021 ACM Summer School on HPC Architectures for Artificial Intelligence and Dedicated Applications.

[2021] Exploiting Page Table Locality for Agile TLB Prefetching paper got accepted at ISCA 2021.

[2020] The presentation of Cost-Effective Instruction TLB Prefetching workshop paper is available on youtube.

[2020] Cost-Effective Instruction TLB Prefetching workshop paper got accepted at YArch 2020 Workshop.

[2019] Received the FPI Doctoral Fellowship by the Spanish Government (MINECO).

Publications

2024

[IPDPS'24] Practically Tackling Memory Bottlenecks of Graph-Processing Workloads

Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Proceedings of the 38th edition of the IEEE International Parallel & Distributed Processing Symposium (IPDPS '24). [pdf] [slides]

[HPCA'24] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering

Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Proceedings of the 30th edition of the International Symposium on High-Performance Computer Architecture (HPCA '24). [pdf] [slides(keynote)] [slides(pdf)]

2023

[ISMM'23] Concurrent GCs and Modern Java Workloads: A Cache Perspective

Maria Carpen-Amarie, Georgios Vavouliotis, Konstantinos Tovletoglou, Boris Grot, Rene Mueller. Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management (ISMM '23). Received the Best Paper Award. [pdf] [slides]

2022

[MICRO'22] Page Size Aware Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. Proceedings of the 55th edition of the IEEE/ACM International Symposium on Microarchitecture (MICRO '22). [pdf] [slides]

2021

[MICRO'21] Morrigan: A Composite Instruction TLB Prefetcher

Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jimenez, Marc Casas. Proceedings of the 54th edition of the IEEE/ACM International Symposium on Microarchitecture (MICRO '21). [pdf] [youtube] [slides] [lightning slides]

[MICRO SRC'21] Leveraging Page Size Information to Enhance Data Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. 2021 ACM Student Research Competition (SRC '21). [pdf] [youtube] [src certificate]

[ACM School'21] Leveraging Page Size Information to Enhance Data Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. 2021 ACM Summer School on HPC Computer Architectures for AI and Dedicated Applications. [pdf] [best poster award]

[ISCA'21] Exploiting Page Table Locality for Agile TLB Prefetching

Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Kozyris, Daniel A. Jimenez, Marc Casas. Proceedings of the 48th edition of the International Symposium on Computer Architecture (ISCA '21). [pdf] [youtube] [slides] [lightning slides] [poster-isca'22]

2020

[YArch'20] Cost-Effective Instruction TLB Prefetching

Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Second Young Architect Workshop (YArch '20). In conjunction with the 25th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '20), Lausanne. [youtube] [pdf]

Doctoral Dissertation

Advanced Hardware Prefetching in Virtual Memory Systems [pdf]

Thesis Statement: Hardware TLB prefetching can reduce the address translation overheads posed with applications with large data and code footprints while exploiting address translation metadata available at the microarchitecture and runtime levels can improve the performance of cache prefetchers.

Contact

E-mail: gvavou5@gmail.com or georgios.vavouliotis@bsc.es or georgios.vavouliotis2@huawei.com

Office: Thurgauerstrasse 80, 8050 Zurich, Switzerland (map)