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Georgios Vavouliotis

Senior Researcher · Huawei Research Center Switzerland

Computer Architecture ML for Architecture Speculation Mechanisms Cache Management Virtual Memory

My name is Georgios (Yorgos) Vavouliotis and I am a Senior Researcher at Huawei Research Center in Zurich. I received my Ph.D. from Universitat Politècnica de Catalunya and Barcelona Supercomputing Center. I also hold a diploma on Electrical and Computer Engineering from the National Technical University of Athens.

My research explores the frontiers of computer architecture and pioneers innovative microarchitectural solutions that address critical computational challenges. I explore advanced techniques for reducing address translation overheads, enhancing cache prefetching performance, and developing smart cache/memory management strategies for complex computing environments and diverse application types. By leveraging AI/ML techniques, I also build intelligent and adaptive components while re-thinking microarchitectural designs for emerging application domains.

My research work has received accolades, including Best Paper and Best Poster awards, and has been mainly featured in top-tier computer architecture conferences, including ISCA, HPCA, MICRO, and ASPLOS.

News

2026
Bumper: Hinting Instruction Usefulness for Robust Unified Caches accepted at ISCA 2026. Paper ISCA'26
2026
Enhancing Instruction Prefetching via Cache and TLB Management accepted at ISCA 2026. Paper ISCA'26
2025
Talk on "Interaction between Virtual Memory and Hardware Prefetching" at the Virtuoso Workshop. Talk
2025
Context-Aware Set Dueling for Dynamic Policy Arbitration accepted at IEEE CAL 2025. Paper CAL'25
2025
Instruction-Aware Cooperative TLB and Cache Replacement Policies accepted at ASPLOS 2025. Paper ASPLOS'25
2025
Received the Future Star Award from Huawei. Award
2025
Received the Innovation Award from Huawei. Award
2025
To Cross, or Not to Cross Pages for Prefetching? accepted at HPCA 2025. Paper HPCA'25
2024
Received the Skyline Award from Huawei. Award
2024
Talk on "Importance of Single-Thread Performance in the Many-Core Era" at SPARKS Workshop (ISCA 2024). Talk
2024
Talk on "Microarchitectural Prediction and Prefetching in Virtual Memory Systems" at AMD Research. Talk
2024
Promoted to Senior Researcher at Huawei Research Center Switzerland.
2024
2023
PhD dissertation "Advanced Hardware Prefetching in Virtual Memory Systems" received the Cum Laude Award. Award
2023
Received the Hisilicon Core Star Award from Huawei. Award
2023
2023
Joined Huawei Research Center Switzerland in Zurich as Postdoctoral Researcher.
2023
Talk on "Hardware Prefetching in Virtual Memory Systems" at the 6th Computing Systems Research Day in Athens. Talk
2022
Page Size Aware Cache Prefetching selected among the most interesting MICRO'22 papers by Denis Bakhvalov. Award
2022
Page Size Aware Cache Prefetching accepted at MICRO 2022. Paper MICRO'22
2022
2021
Talk on "Morrigan: A Composite Instruction TLB Prefetcher" at Huawei Zurich. Talk
2021
Leveraging Page Size Information to Enhance Data Cache Prefetching received the Best Poster Award at the 2021 ACM Summer School on HPC Architectures for AI and Dedicated Applications. Award
2021
Morrigan: A Composite Instruction TLB Prefetcher accepted at MICRO 2021. Paper MICRO'21
2021
Exploiting Page Table Locality for Agile TLB Prefetching accepted at ISCA 2021. Paper ISCA'21
2020
Talk on "Cost-Effective Instruction TLB Prefetching" at YArch 2020, available on YouTube. Talk
2020
Cost-Effective Instruction TLB Prefetching accepted at YArch 2020. Paper

Publications

2026
ISCA'26 Spotlight
Bumper: Hinting Instruction Usefulness for Robust Unified Caches
Georgios Vavouliotis, Tom Rollet, Davide Basilio Bartolini, Boris Grot, Leeor Peled, Yang Lixia.
53rd ACM/IEEE International Symposium on Computer Architecture (ISCA '26).
@inproceedings{vavouliotis2026bumper,
  author       = {Vavouliotis, Georgios and Rollet, Tom and Bartolini, Davide Basilio and
                  Grot, Boris and Peled, Leeor and Lixia, Yang},
  title        = {Bumper: Hinting Instruction Usefulness for Robust Unified Caches},
  booktitle    = {2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA)},
  year         = {2026},
  organization = {IEEE}
}
ISCA'26
Enhancing Instruction Prefetching via Cache and TLB Management
Alexandre Valentin Jamet, Georgios Vavouliotis, Martí Torrents, Dimitrios Chasapis, Marc Casas.
53rd ACM/IEEE International Symposium on Computer Architecture (ISCA '26).
@inproceedings{jamet2026enhancing,
  author       = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and Torrents, Mart\'{i} and
                  Chasapis, Dimitrios and Casas, Marc},
  title        = {Enhancing Instruction Prefetching via Cache and {TLB} Management},
  booktitle    = {2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA)},
  year         = {2026},
  organization = {IEEE}
}
2025
IEEE CAL'25
Diamantis Patsidis, Georgios Vavouliotis.
IEEE Computer Architecture Letters (CAL), Oct 2025.
@article{patsidis2025context,
  author    = {Patsidis, Diamantis and Vavouliotis, Georgios},
  title     = {Context-Aware Set Dueling for Dynamic Policy Arbitration},
  journal   = {IEEE Computer Architecture Letters},
  year      = {2025},
  publisher = {IEEE}
}
ASPLOS'25 Spotlight
HiPEAC 2025 Paper Award
Georgios Vavouliotis*, Dimitrios Chasapis*, Daniel A. Jimenez, Marc Casas. (*Equally contributed)
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '25).
@inproceedings{vavouliotis2025instruction,
  author    = {Vavouliotis, Georgios and Chasapis, Dimitrios and Jimenez, Daniel A. and Casas, Marc},
  title     = {Instruction-Aware Cooperative {TLB} and Cache Replacement Policies},
  booktitle = {Proceedings of the 30th ACM International Conference on Architectural Support
               for Programming Languages and Operating Systems (ASPLOS)},
  year      = {2025}
}
HPCA'25 Spotlight
HiPEAC 2025 Paper Award
Georgios Vavouliotis, Marti Torrents, Boris Grot, Kleovoulos Kalaitzidis, Leeor Peled, Marc Casas.
31st IEEE International Symposium on High-Performance Computer Architecture (HPCA '25).
@inproceedings{vavouliotis2025cross,
  author       = {Vavouliotis, Georgios and Torrents, Marti and Grot, Boris and
                  Kalaitzidis, Kleovoulos and Peled, Leeor and Casas, Marc},
  title        = {To Cross, or Not to Cross Pages for Prefetching?},
  booktitle    = {2025 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
  year         = {2025},
  organization = {IEEE}
}
2024
HPCA'24
HiPEAC 2024 Paper Award
Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas.
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA '24).
@inproceedings{jamet2024two,
  author       = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and
                  Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
  title        = {A Two Level Neural Approach Combining Off-Chip Prediction with
                  Adaptive Prefetch Filtering},
  booktitle    = {2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
  year         = {2024},
  organization = {IEEE}
}
IPDPS'24
Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas.
38th IEEE International Parallel & Distributed Processing Symposium (IPDPS '24).
@inproceedings{jamet2024practically,
  author       = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and
                  Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
  title        = {Practically Tackling Memory Bottlenecks of Graph-Processing Workloads},
  booktitle    = {2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
  year         = {2024},
  organization = {IEEE}
}
2023
ISMM'23
Best Paper Award
Maria Carpen-Amarie, Georgios Vavouliotis, Konstantinos Tovletoglou, Boris Grot, Rene Mueller.
ACM SIGPLAN International Symposium on Memory Management (ISMM '23).
@inproceedings{carpen2023concurrent,
  author    = {Carpen-Amarie, Maria and Vavouliotis, Georgios and Tovletoglou, Konstantinos and
               Grot, Boris and Mueller, Rene},
  title     = {Concurrent {GCs} and Modern {Java} Workloads: {A} Cache Perspective},
  booktitle = {Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management (ISMM)},
  year      = {2023}
}
2022
MICRO'22 Spotlight
HiPEAC 2022 Paper Award
Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas.
55th IEEE/ACM International Symposium on Microarchitecture (MICRO '22).
@inproceedings{vavouliotis2022page,
  author       = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
                  Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
  title        = {Page Size Aware Cache Prefetching},
  booktitle    = {2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  year         = {2022},
  organization = {IEEE}
}
2021
MICRO'21 Spotlight
HiPEAC 2021 Paper Award
Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jimenez, Marc Casas.
54th IEEE/ACM International Symposium on Microarchitecture (MICRO '21).
@inproceedings{vavouliotis2021morrigan,
  author    = {Vavouliotis, Georgios and Alvarez, Lluc and Grot, Boris and
               Jimenez, Daniel A. and Casas, Marc},
  title     = {Morrigan: {A} Composite Instruction {TLB} Prefetcher},
  booktitle = {Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  year      = {2021}
}
ISCA'21 Spotlight
HiPEAC 2021 Paper Award
Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Kozyris, Daniel A. Jimenez, Marc Casas.
48th IEEE/ACM International Symposium on Computer Architecture (ISCA '21).
@inproceedings{vavouliotis2021exploiting,
  author       = {Vavouliotis, Georgios and Alvarez, Lluc and Karakostas, Vasileios and
                  Nikas, Konstantinos and Kozyris, Nectarios and Jimenez, Daniel A. and Casas, Marc},
  title        = {Exploiting Page Table Locality for Agile {TLB} Prefetching},
  booktitle    = {2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)},
  year         = {2021},
  organization = {IEEE}
}
MICRO SRC'21
Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas.
2021 ACM Student Research Competition (SRC '21), at MICRO '21.
@misc{vavouliotis2021leveraging_src,
  author = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
            Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
  title  = {Leveraging Page Size Information to Enhance Data Cache Prefetching},
  year   = {2021},
  note   = {ACM Student Research Competition (SRC) at MICRO 2021}
}
ACM School'21
Best Poster Award
Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas.
2021 ACM Summer School on HPC Computer Architectures for AI and Dedicated Applications.
@misc{vavouliotis2021leveraging_acm,
  author = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
            Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
  title  = {Leveraging Page Size Information to Enhance Data Cache Prefetching},
  year   = {2021},
  note   = {2021 ACM Summer School on HPC Computer Architectures for AI and Dedicated Applications}
}
2020
YArch'20
Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas.
Second Young Architect Workshop (YArch '20), co-located with ASPLOS '20, Lausanne.
@misc{vavouliotis2020cost,
  author = {Vavouliotis, Georgios and Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
  title  = {Cost-Effective Instruction {TLB} Prefetching},
  year   = {2020},
  note   = {Second Young Architect Workshop (YArch 2020), co-located with ASPLOS 2020}
}
Doctoral Dissertation
Hardware TLB prefetching can reduce the address translation overheads posed by applications with large data and code footprints, while exploiting address translation metadata available at the microarchitecture and runtime levels can improve the performance of cache prefetchers.

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