Georgios Vavouliotis
Senior Researcher · Huawei Research Center Switzerland
My name is Georgios (Yorgos) Vavouliotis and I am a Senior Researcher at Huawei Research Center in Zurich. I received my Ph.D. from Universitat Politècnica de Catalunya and Barcelona Supercomputing Center. I also hold a diploma on Electrical and Computer Engineering from the National Technical University of Athens.
My research explores the frontiers of computer architecture and pioneers innovative microarchitectural solutions that address critical computational challenges. I explore advanced techniques for reducing address translation overheads, enhancing cache prefetching performance, and developing smart cache/memory management strategies for complex computing environments and diverse application types. By leveraging AI/ML techniques, I also build intelligent and adaptive components while re-thinking microarchitectural designs for emerging application domains.
My research work has received accolades, including Best Paper and Best Poster awards, and has been mainly featured in top-tier computer architecture conferences, including ISCA, HPCA, MICRO, and ASPLOS.
News
Publications
@inproceedings{vavouliotis2026bumper,
author = {Vavouliotis, Georgios and Rollet, Tom and Bartolini, Davide Basilio and
Grot, Boris and Peled, Leeor and Lixia, Yang},
title = {Bumper: Hinting Instruction Usefulness for Robust Unified Caches},
booktitle = {2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA)},
year = {2026},
organization = {IEEE}
}
@inproceedings{jamet2026enhancing,
author = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and Torrents, Mart\'{i} and
Chasapis, Dimitrios and Casas, Marc},
title = {Enhancing Instruction Prefetching via Cache and {TLB} Management},
booktitle = {2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA)},
year = {2026},
organization = {IEEE}
}
@article{patsidis2025context,
author = {Patsidis, Diamantis and Vavouliotis, Georgios},
title = {Context-Aware Set Dueling for Dynamic Policy Arbitration},
journal = {IEEE Computer Architecture Letters},
year = {2025},
publisher = {IEEE}
}
@inproceedings{vavouliotis2025instruction,
author = {Vavouliotis, Georgios and Chasapis, Dimitrios and Jimenez, Daniel A. and Casas, Marc},
title = {Instruction-Aware Cooperative {TLB} and Cache Replacement Policies},
booktitle = {Proceedings of the 30th ACM International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS)},
year = {2025}
}
@inproceedings{vavouliotis2025cross,
author = {Vavouliotis, Georgios and Torrents, Marti and Grot, Boris and
Kalaitzidis, Kleovoulos and Peled, Leeor and Casas, Marc},
title = {To Cross, or Not to Cross Pages for Prefetching?},
booktitle = {2025 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
year = {2025},
organization = {IEEE}
}
@inproceedings{jamet2024two,
author = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and
Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
title = {A Two Level Neural Approach Combining Off-Chip Prediction with
Adaptive Prefetch Filtering},
booktitle = {2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)},
year = {2024},
organization = {IEEE}
}
@inproceedings{jamet2024practically,
author = {Jamet, Alexandre Valentin and Vavouliotis, Georgios and
Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
title = {Practically Tackling Memory Bottlenecks of Graph-Processing Workloads},
booktitle = {2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
year = {2024},
organization = {IEEE}
}
@inproceedings{carpen2023concurrent,
author = {Carpen-Amarie, Maria and Vavouliotis, Georgios and Tovletoglou, Konstantinos and
Grot, Boris and Mueller, Rene},
title = {Concurrent {GCs} and Modern {Java} Workloads: {A} Cache Perspective},
booktitle = {Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management (ISMM)},
year = {2023}
}
@inproceedings{vavouliotis2022page,
author = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
title = {Page Size Aware Cache Prefetching},
booktitle = {2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)},
year = {2022},
organization = {IEEE}
}
@inproceedings{vavouliotis2021morrigan,
author = {Vavouliotis, Georgios and Alvarez, Lluc and Grot, Boris and
Jimenez, Daniel A. and Casas, Marc},
title = {Morrigan: {A} Composite Instruction {TLB} Prefetcher},
booktitle = {Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
year = {2021}
}
@inproceedings{vavouliotis2021exploiting,
author = {Vavouliotis, Georgios and Alvarez, Lluc and Karakostas, Vasileios and
Nikas, Konstantinos and Kozyris, Nectarios and Jimenez, Daniel A. and Casas, Marc},
title = {Exploiting Page Table Locality for Agile {TLB} Prefetching},
booktitle = {2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)},
year = {2021},
organization = {IEEE}
}
@misc{vavouliotis2021leveraging_src,
author = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
title = {Leveraging Page Size Information to Enhance Data Cache Prefetching},
year = {2021},
note = {ACM Student Research Competition (SRC) at MICRO 2021}
}
@misc{vavouliotis2021leveraging_acm,
author = {Vavouliotis, Georgios and Chancon, Gino and Alvarez, Lluc and
Gratz, Paul V. and Jimenez, Daniel A. and Casas, Marc},
title = {Leveraging Page Size Information to Enhance Data Cache Prefetching},
year = {2021},
note = {2021 ACM Summer School on HPC Computer Architectures for AI and Dedicated Applications}
}
@misc{vavouliotis2020cost,
author = {Vavouliotis, Georgios and Alvarez, Lluc and Jimenez, Daniel A. and Casas, Marc},
title = {Cost-Effective Instruction {TLB} Prefetching},
year = {2020},
note = {Second Young Architect Workshop (YArch 2020), co-located with ASPLOS 2020}
}
Hardware TLB prefetching can reduce the address translation overheads posed by applications with large data and code footprints, while exploiting address translation metadata available at the microarchitecture and runtime levels can improve the performance of cache prefetchers.