Georgios Vavouliotis

Georgios Vavouliotis

Senior Researcher @ Huawei Zurich Research Center

A Few Words About Me

My name is Georgios (Yorgos) Vavouliotis and I am a Senior Researcher at Huawei Research Center in Zurich. I received my Ph.D. from Universitat Politècnica de Catalunya (UPC) and Barcelona Supercomputing Center (BSC-CNS). I also hold a diploma on Electrical and Computer Engineering from the National Technical University of Athens (NTUA).

My research explores the frontiers of computer architecture and pioneers innovative microarchitectural solutions that address critical computational challenges. I explore advanced techniques for reducing address translation overheads, enhancing cache prefetching performance, and developing smart cache/memory management strategies for complex computing environments and diverse application types. By leveraging AI/ML techniques, I aim to build intelligent and adaptive microarchitectural components while re-thinking microarchitectural designs for emerging application domains.

My research work has received accolades, including Best Paper and Best Poster awards, and has been featured in top-tier computer architecture conferences, including ISCA, HPCA, MICRO, and ASPLOS.

You can find my research vision for the next years here [updated February 2023].

Recent News

[2025] Instruction-Aware Cooperative TLB and Cache Replacement Policies accepted at ASPLOS 2025.

[2025] I received the Future Star Award from Huawei for my research contributions.

[2025] To Cross, or Not to Cross Pages for Prefetching? accepted at HPCA 2025.

[2025] Participation in Major Program Committees (PCs) for 2025 (so far): ISCA'25 Industry Track.

[2024] I received the Skyline Award from Huawei.

[2024] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering received the HiPEAC 2024 Paper Award.

[2024] Participation in Major Program Committees (PCs) for 2024: ASPLOS'25, HPCA'25, MICRO’24, ISCA'24 Industry Track, HPCA'24 (AE).

[2024] I'll give a talk about "Importance of Single-Thread Performance in the Many-Core Era" at SPARKS Workshop (ISCA 2024).

[2024] I'll give a talk about Microarchitectural Prediction and Prefetching in Virtual Memory Systems at AMD Research.

[2024] I have been promoted to Senior Researcher at Huawei Zurich.

[2024] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering accepted at HPCA 2024.

[2023] I will serve as Website Chair at ISCA'24.

[2023] I defended my Ph.D. "Advanced Hardware Prefetching in Virtual Memory Systems" receiving the Cum Laude Award.

[2023] I received the Hisilicon Core Star Award from Huawei.

[2023] Concurrent GCs and Modern Java Workloads: A Cache Perspective received the Best Paper Award at ISMM'23.

[2023] Concurrent GCs and Modern Java Workloads: A Cache Perspective accepted at ISMM'23.

[2023] I joined Huawei ZRC in Zurich as Postdoctoral Researcher.

[2023] I'll give a talk about Hardware Prefetching in Virtual Memory Systems at the 6th Computing Systems Research Day in Athens.

[2022] Page Size Aware Cache Prefetching was selected among the most interesting MICRO'22 papers from Denis Bakhvalov.

[2022] Page Size Aware Cache Prefetching accepted at MICRO 2022.

[2021] Morrigan: A Composite Instruction TLB Prefetcher accepted at MICRO 2021.

[2021] Leveraging Page Size Information to Enhance Data Cache Prefetching received the Best Poster Award at 2021 ACM Summer School on HPC Architectures for Artificial Intelligence and Dedicated Applications, and was awarded with 500$.

[2021] Exploiting Page Table Locality for Agile TLB Prefetching paper accepted at ISCA 2021.

[2025] Instruction-Aware Cooperative TLB and Cache Replacement Policies accepted at ASPLOS 2025.

[2025] I received the Future Star Award from Huawei for my research contributions.

[2025] To Cross, or Not to Cross Pages for Prefetching? accepted at HPCA 2025.

[2024] I received the Skyline Award from Huawei.

[2024] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering received the HiPEAC 2024 Paper Award.

[2024] I will serve in the ISCA 2025 Industry Track Program Committee (PC).

[2024] I'll give a talk about "Importance of Single-Thread Performance in the Many-Core Era" at SPARKS Workshop (ISCA 2024).

[2024] I will attend ISCA 2024. See you all in Buenos Aires!

[2024] I'll give a talk about Microarchitectural Prediction and Prefetching in Virtual Memory Systems at AMD Research.

[2024] I have been promoted to Senior Researcher at Huawei Zurich.

[2024] I will serve in the ASPLOS 2025 Program Committee (PC).

[2024] I will serve in the HPCA 2025 Program Committee (PC).

[2024] I will serve in the MICRO 2024 Program Committee (PC).

[2024] I will serve in the ISCA 2024 Industry Track Program Committee (PC).

[2024] Practically Tackling Memory Bottlenecks of Graph-Processing Workloads accepted at IPDPS 2024.

[2024] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering accepted at HPCA 2024.

[2024] I will serve in the Program Committee (PC) of the European Conference on Parallel and Distributed Computing (Euro-Par’24).

[2023] I will serve in the Artifact Evaluation (AE) Committee of HPCA'24.

[2023] I will serve as Website Chair at ISCA'24.

[2023] I defended my Ph.D. "Advanced Hardware Prefetching in Virtual Memory Systems" receiving the Cum Laude Award.

[2023] I received the Hisilicon Core Star Award from Huawei.

[2023] Concurrent GCs and Modern Java Workloads: A Cache Perspective received the Best Paper Award at ISMM'23.

[2023] Concurrent GCs and Modern Java Workloads: A Cache Perspective accepted at ISMM'23.

[2023] Page Size Aware Cache Prefetching received the HiPEAC 2022 Paper Award.

[2023] I joined Huawei ZRC in Zurich as Postdoctoral Researcher.

[2023] I'll give a talk about Hardware Prefetching in Virtual Memory Systems at the 6th Computing Systems Research Day in Athens.

[2022] Page Size Aware Cache Prefetching was selected among the most interesting MICRO'22 papers from Denis Bakhvalov.

[2022] I received the MICRO'22 Student Travel Grant and I'll physically attend the MICRO'22 conference in Chicago.

[2022] Page Size Aware Cache Prefetching accepted at MICRO 2022.

[2022] I presented a poster of our ISCA'21 paper Exploiting Page Table Locality for Agile TLB Prefetching at ISCA'22 in New York.

[2022] I received the ISCA'22 Student Travel Grant and I'll physically attend the ISCA'22 conference in New York.

[2022] Morrigan received the HiPEAC 2021 Paper Award.

[2022] Exploiting Page Table Locality for Agile TLB Prefetching received the HiPEAC 2021 Paper Award.

[2021] I'll give a talk about Morrigan at Huawei Zurich.

[2021] I'm joining the Huawei Zurich Research Center for a 6-month internship to work on memory management.

[2021] Leveraging Page Size Information to Enhance Data Cache Prefetching was selected to participate in the 2021 ACM Student Research Competition (SRC). (certificate)

[2021] Morrigan: A Composite Instruction TLB Prefetcher accepted at MICRO 2021.

[2021] I'll attend the 2021 ACM Summer School on HPC Architectures for Artificial Intelligence and Dedicated Applications.

[2021] Exploiting Page Table Locality for Agile TLB Prefetching paper accepted at ISCA 2021.

[2020] The presentation of Cost-Effective Instruction TLB Prefetching workshop paper is available on youtube.

[2020] Cost-Effective Instruction TLB Prefetching workshop paper accepted at YArch 2020 Workshop.

[2019] Received the FPI Doctoral Fellowship by the Spanish Government (MINECO).

Publications

2025

[ASPLOS'25] Instruction-Aware Cooperative TLB and Cache Replacement Policies

Georgios Vavouliotis*, Dimitrios Chasapis*, Daniel A. Jimenez, Marc Casas. Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '25). [pdf] [slides] [*Equally contributed authors]

[HPCA'25] To Cross, or Not to Cross Pages for Prefetching?

Georgios Vavouliotis, Marti Torrents, Boris Grot, Kleovoulos Kalaitzidis, Leeor Peled, Marc Casas. Proceedings of the 31st edition of the International Symposium on High-Performance Computer Architecture (HPCA'25). [pdf] [slides]

2024

[IPDPS'24] Practically Tackling Memory Bottlenecks of Graph-Processing Workloads

Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Proceedings of the 38th edition of the IEEE International Parallel & Distributed Processing Symposium (IPDPS '24). [pdf] [slides]

[HPCA'24] A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering

Alexandre Valentin Jamet, Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Proceedings of the 30th edition of the International Symposium on High-Performance Computer Architecture (HPCA '24). [pdf] [slides(keynote)] [slides(pdf)]

2023

[ISMM'23] Concurrent GCs and Modern Java Workloads: A Cache Perspective

Maria Carpen-Amarie, Georgios Vavouliotis, Konstantinos Tovletoglou, Boris Grot, Rene Mueller. Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management (ISMM '23). Received the Best Paper Award. [pdf] [slides]

2022

[MICRO'22] Page Size Aware Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. Proceedings of the 55th edition of the IEEE/ACM International Symposium on Microarchitecture (MICRO '22). [pdf] [slides]

2021

[MICRO'21] Morrigan: A Composite Instruction TLB Prefetcher

Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jimenez, Marc Casas. Proceedings of the 54th edition of the IEEE/ACM International Symposium on Microarchitecture (MICRO '21). [pdf] [youtube] [slides] [lightning slides]

[MICRO SRC'21] Leveraging Page Size Information to Enhance Data Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. 2021 ACM Student Research Competition (SRC '21). [pdf] [youtube] [src certificate]

[ACM School'21] Leveraging Page Size Information to Enhance Data Cache Prefetching

Georgios Vavouliotis, Gino Chancon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jimenez, Marc Casas. 2021 ACM Summer School on HPC Computer Architectures for AI and Dedicated Applications. [pdf] [best poster award]

[ISCA'21] Exploiting Page Table Locality for Agile TLB Prefetching

Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Kozyris, Daniel A. Jimenez, Marc Casas. Proceedings of the 48th edition of the International Symposium on Computer Architecture (ISCA '21). [pdf] [youtube] [slides] [lightning slides] [poster-isca'22]

2020

[YArch'20] Cost-Effective Instruction TLB Prefetching

Georgios Vavouliotis, Lluc Alvarez, Daniel A. Jimenez, Marc Casas. Second Young Architect Workshop (YArch '20). In conjunction with the 25th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '20), Lausanne. [youtube] [pdf]

Doctoral Dissertation

Advanced Hardware Prefetching in Virtual Memory Systems [pdf]

Thesis Statement: Hardware TLB prefetching can reduce the address translation overheads posed with applications with large data and code footprints while exploiting address translation metadata available at the microarchitecture and runtime levels can improve the performance of cache prefetchers.

Contact

E-mail: gvavou5@gmail.com or georgios.vavouliotis@huawei.com

Office: Thurgauerstrasse 80, 8050 Zurich, Switzerland (map)